Download Analog Circuit Design: High-speed Clock and Data Recovery, by Michiel Steyaert, Arthur H.M. van Roermund, Herman Casier PDF
By Michiel Steyaert, Arthur H.M. van Roermund, Herman Casier
Analog Circuit layout comprises the contribution of 18 tutorials of the seventeenth workshop on Advances in Analog Circuit layout. every one half discusses a particular to-date subject on new and priceless layout rules within the sector of analog circuit layout. every one half is gifted by means of six specialists in that box and state-of-the-art details is shared and overviewed. This ebook is quantity 17 during this winning sequence of Analog Circuit layout.
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Extra info for Analog Circuit Design: High-speed Clock and Data Recovery, High-performance Amplifiers, Power Management
35 Figure 10 illustrates possible loop filter implementations using passive components. The advantage of the passive approach is that good noise performance can be achieved with minimal power consumption, and that the overall PLL implementation is simplified by minimizing the amount of active circuitry. These advantages have led to widespread use of the RC network shown for the Type II, Order 2 implementation in Figure 10. Passive approaches are rarely used for higher order loop filter implementations due to the awkwardness of using inductors.
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W. Rhee and A. Ali, “An on-chip phase-compensation technique in fractional-N frequency synthesis,” in IEEE Proceedings of ISCAS, vol. 3, May 1999, pp. 363-366. T. A. Riley, M. Copeland, and T. Kwasniewski, “Delta-sigma modulation in fractional-N frequency synthesis,” IEEE Journal of Solid-State Circuits, vol. 28, pp. 553-559, May 1993. B. Miller and R. Conley, “A multiple modulator fractional divider,” IEEE Transactions on Instrumentation and Measurement, vol. 40, pp. 578-583, June 1991. W. Rhee, B.